Digital-to-analog converter (DAC) circuitry is used in numerous electronics application. A DAC requires a finite amount of time to sense input codes and convert the codes to an analog value (e.g., current or voltage) that the DAC then provides at its output. A finite amount of time is also required for the output of the DAC to stabilize or settle upon the analog value. These time elements establish an upper boundary on the performance bandwidth of the digital-to-analog conversion process.
A current steering DAC architecture is particularly desirable for speed advantages over other architectures. A current steering DAC generates a differential current output that is typically applied to a current-to-voltage converting amplifier to produce a differential voltage output. Current steering DACs, however, tend to have relatively poor dynamic performance.
Transient voltages will appear at the DAC output due to the periodic code updates applied to the DAC. Although the effect is dependent upon the specific DAC architecture, the transients frequently manifest as a “smearing” of the analog output. This smearing can introduce distortion in a baseband signal even after application of a reconstruction filter. More succinctly, input code transitions for current steering DACs frequently result in a “glitch” in the output signal.
Various attempts have been made to reduce or eliminate the glitch for current steering DACs. Generally, the attempts focus on reducing the height or the width of glitch.
For example, one current steering DAC architecture uses thermometer encoding for the DAC internal current sources. Although this approach ensures that the height of the glitch is less than the smallest DAC current step size, one disadvantage of such an architecture is that 2N current sources are required, where N is the number of bits of resolution.
Another approach is to use a row of latches to resynchronize the edges of the input binary codes at the DAC input such that the delays between different codes are minimized. This approach attempts to reduce the width of the glitch. Aside from noise and area impact, this approach does not fully eliminate the glitch due to the residual mismatch in latch gate delays and DAC switches.